Semiconductor Engineering

Wafer Bin Map Defect Classification Using Semi-Supervised Learning

A new technical paper titled “Semi-Supervised Learning with Wafer-Specific Augmentations for Wafer Defect Classification” was published by researchers at Korea University. “Semi-supervised learning ...
Nature

Semiconductor Wafer Defect Pattern Recognition and Classification

Semiconductor wafer defect pattern recognition and classification is a crucial area of research that underpins yield enhancement and quality assurance in microelectronics manufacturing. The discipline ...
Semiconductor Engineering

Hunting For Macro Defects

Detecting macro-defects early in the wafer processing flow is vital for yield and process improvement, and it is driving innovations in both inspection techniques and wafer test map analysis. At the ...
EurekAlert!

Optical wafer defect inspection at the 10 nm technology node and beyond

Defect inspection scientists from Huazhong University of Science and Technology, Harbin Institute of Technology and The Chinese University of Hong Kong make a thorough review of new perspectives and ...
ZDNet

Future of chip making to lean heavily on AI for spotting defects, says Applied Materials

To make the top-of-the-line chips for Apple's iPhone, such as the A14, or Nvidia's A100 series AI processors, with billions of transistors, it takes a factory that costs $16 billion to build and ...