EDN

Building a better memory controller: architectural performance exploration of an AXI memory controller

Communicationbetween processors and memories is often a major bottleneck, making the designof the memory controller a critical task in determining overall system-levelperformance. The memory ...
EDN

DDR3 memory interface controller IP speeds data processing applications

DDR3 memory systems can provide a significant performance boost to a variety of data processing applications. However, compared to previous generations (DDR and DDR2), DDR3 memory devices have some ...
Business Wire

Rambus Boosts AI Performance with 9.6 Gbps HBM3 Memory Controller IP

SAN JOSE, Calif.--(BUSINESS WIRE)--Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced that the Rambus HBM3 Memory Controller IP now ...
Electronic Design

Key Challenges in SSD Controller Development

A new generation of solid-state drive (SSD) controllers has turned the SSD business on end by enabling enterprise-class performance, reliability, and endurance with standard NAND flash memory. In this ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
Semiconductor Engineering

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
TweakTown

China's Innosilicon LPDDR6/5X memory controller IP delivered to first customers, up to 14.4Gbps

Chinese chip maker Innosilicon has announced its new LPDDR6/5X memory controller IP provided to its first customers in China, ...
Design-Reuse

Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory ...

Digital Blocks is a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers requiring best-in-class IP for AMBA ...

Innosilicon First To Ship LPDDR6 Memory IP At Blistering 14.4Gbps Speeds

This isn't about memory chips, but implementable logic blocks for chip vendors, and it's a significant milestone for the ...
CNET

Why Intel doesn't include a memory controller on its chips

Michael Kanellos is editor at large at CNET News.com, where he covers hardware, research and development, start-ups and the tech industry overseas. If you want to know why Intel doesn't include a ...