IEEE

Hardware Circuits and Systems Design for Post-Quantum Cryptography—A Tutorial Brief

Abstract: Due to the increasing threats from possible large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from various communities recently. In particular, ...
Digi Times

Meta accelerates AI ASIC roll-out as Broadcom secures four-generation chip design deal

Meta recently announced plans to launch four generations of ASIC product lines over the next two years, including the already mass-produced MTIA 300 and upcoming MTIA 400, 450, and 500 chips. These ...
IEEE

Design and Implementation of a Compact Digital Frequency Modulator in an ASIC

Abstract: In this paper, we present a digital frequency modulator designed and fabricated within the Tiny Tapeout application-specific integrated circuit (ASIC) framework, which serves as a hands-on ...
Digi Times

GUC outperforms as design services navigate volatility

Global Unichip Corp. (GUC) emerged as a standout performer in the design services sector for February 2026, reporting revenue of NT$3.4 million (approx. US$106,454). This represents a powerful 60.15% ...
Design-Reuse

CAST Introduces 400 Gbps UDP/IP Hardware Stack IP Core for High-Performance ASIC Designs

New standalone core delivers ultra-high-throughput, low-latency UDP/IP offload for data centers, AI training, media streaming, HPC, and real-time systems. Woodcliff Lake, NJ — March 10, 2026 — CAST, a ...
Semiconductor Engineering

A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)

A new technical paper, “NL2GDS: LLM-aided interface for Open Source Chip Design,” was published by researchers at University of Bristol and Rutherford Appleton Laboratory. “The growing complexity of ...